ICS1893Y-10 Datasheet, PDF (37/150 Pages) –

ICS1893Y-10 - Release
Chapter 5 Interface Overviews
5.8 Status Interface
The ICS1893Y-10 LSTA pin provides a Link Status, and its LOCK pin provides a Stream Cipher Locking
Status. In addition, as listed in Table 5-5, the ICS1893Y-10 provides five multi-function configuration pins
that report the results of continual link monitoring by providing signals that are intended for driving LEDs.
(For the pin numbers, see Table 8.3.2.)
Table 5-5. Pins for Monitoring the Data Link
Pin
P0AC
P1CL
P2LI
P3TD
P4RD
LED Driven by the Pin’s Output Signal
AC (Link Activity) LED
CL (Collisions) LED
LI (Link Integrity) LED
TD (Transmit Data) LED
RD (Receive Data) LED
Note:
1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input
that is sampled when the ICS1893Y-10 exits the reset state. After sampling is complete, these pins are
output pins that can drive status LEDs.
2. A software reset does not affect the state of a multi-function configuration pin. During a software reset,
all multi-function configuration pins are outputs.
3. Each multi-function configuration pin must be pulled either up or down with a resistor to establish the
address of the ICS1893Y-10. LEDs may be placed in series with these resistors to provide a
designated status indicator as described in Table 5-5.
Caution: All pins listed in Table 5-5 must not float.
4. As outputs, the asserted state of a multi-function configuration pin is the inverse of the sense sampled
during reset. This inversion provides a signal that can illuminate an LED during an asserted state. For
example, if a multi-function configuration pin is pulled down to ground through an LED and a
current-limiting resistor, then the sampled sense of the input is low. To illuminate this LED for the
asserted state, the output is driven high.
5. Adding 10KΩ resistors across the LEDs ensures the PHY address is fully defined during slow VDD
power-ramp conditions.
6. PHY address 00 tri-states the MII interface. (Do not select PHY address 00 unless you want the MII
tri-stated.
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
37
January, 2004