ICS1893Y-10 Datasheet, PDF (112/150 Pages) –

ICS1893Y-10 Data Sheet - Release
Chapter 8 Pin Diagram, Listings, and Descriptions
Table 8-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued)
Pin
Name
MDIO
RXCLK
Pin
Number
30
38
Pin
Type
Input/
Output
Output
Pin Description
Management Data Input/Output.
The signal on this pin can be tri-stated and can be driven by one of the
following:
• A Station Management Entity (STA), to transfer command and data
information to the registers of the ICS1893Y-10.
• The ICS1893Y-10, to transfer status information.
All transfers and sampling are synchronous with the signal on the MDC
pin.
Note: If the ICS1893Y-10 is to be used in an application that uses the
mechanical MII specification, MDIO must have a 1.5 kΩ ±5%
pull-up resistor at the ICS1893Y-10 end and a 2 kΩ ±5% pull-down
resistor at the station management end. (These resistors enable
the station management to determine if the connection is intact.)
Receive Clock.
The ICS1893Y-10 sources the RXCLK to the MAC/repeater interface. The
ICS1893Y-10 uses RXCLK to synchronize the signals on the following
pins: RXD[3:0], RXDV, and RXER. The following table contrasts the
behavior on the RXCLK pin when the mode for the ICS1893Y-10 is either
10Base-T or 100Base-TX.
10Base-T
100Base-TX
The RXCLK frequency is 2.5
MHz.
The RXCLK frequency is 25 MHz.
The ICS1893Y-10 generates its
RXCLK from the MDI data stream
using a digital PLL. When the MDI
data stream terminates, the PLL
continues to operate,
synchronously referenced to the
last packet received.
The ICS1893Y-10 generates its
RXCLK from the MDI data stream
while there is a valid link (that is,
either data or IDLEs). In the
absence of a link, the
ICS1893Y-10 uses the REF_IN
clock to generate the RXCLK.
The ICS1893Y-10 switches
between clock sources during the
period between when its CRS is
asserted and prior to its RXDV
being asserted. While the
ICS1893Y-10 is locking onto the
incoming data stream, a clock
phase change of up to 360
degrees can occur.
While the ICS1893Y-10 is
bringing up a link, a clock phase
change of up to 360 degrees can
occur.
The RXCLK aligns once per
packet.
The RXCLK aligns once, when
the link is being established.
Note: The signal on the RXCLK pin is conditioned by the RXTRI pin.
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
112
January, 2004