ICS1893Y-10 Datasheet, PDF (132/150 Pages) –

ICS1893Y-10 Data Sheet - Release
Chapter 9 DC and AC Operating Conditions
9.5.8 10M Serial Interface: Receive Latency
Table 9-15 lists the significant time periods for the 10M Serial Interface timing. The time periods consist of
timings of signals on the following pins:
• TP_RX (the MDI mapping of the 10M/100M MII TP_RXP and TP_RXN pins)
• 10RCLK (the 10M Serial Interface mapping of the 10M/100M MII RXCLK pins)
• 10RD (the 10M Serial Interface mapping of the 10M/100M MII RXD0 pins)
Figure 9-9 shows the timing diagram for the time periods.
Table 9-15. 10M Serial Interface Receive Latency Timing
Time
Period
Parameter
t1 TP_RX Input to 10RD Delay
Conditions
Min. Typ. Max. Units
10M Serial Interface – 3.6 4 Bit times
Figure 9-9. 10M Serial Interface Receive Latency Timing
TP_RX
10RCLK
10RD
Bit A
Bit B
Bit A
Bit B
t1
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
132
January, 2004