ICS1893Y-10 Datasheet, PDF (113/150 Pages) –

ICS1893Y-10 - Release
Chapter 8 Pin Diagram, Listings, and Descriptions
Table 8-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued)
Pin
Name
RXD0,
RXD1,
RXD2,
RXD3
RXDV
RXER
Pin
Number
35,
34,
33,
32
36
39
Pin
Type
Output
Output
Output
Pin Description
Receive Data 0–3.
• RXD0 is the least-significant bit and RXD3 is the most-significant bit of
the MII receive data nibble.
• While the ICS1893Y-10 asserts RXDV, the ICS1893Y-10 transfers the
receive data signals on the RXD0–RXD3 pins to the MAC/Repeater
Interface synchronously on the rising edges of RXCLK.
Receive Data Valid.
The ICS1893Y-10 asserts RXDV to indicate to the MAC/repeater that data
is available on the MII Receive Bus (RXD[3:0]). The ICS1893Y-10:
• Asserts RXDV after it detects and recovers the Start-of-Stream
delimiter, /J/K/. (For the timing reference, see Chapter 9.5.6, “MII /
100M Stream Interface: Synchronous Receive Timing”.)
• De-asserts RXDV after it detects either the End-of-Stream delimiter
(/T/R/) or a signal error.
Note: RXDV is synchronous with the Receive Data Clock, RXCLK.
Receive Error.
When the MAC/Repeater Interface is in:
• 10M MII mode, RXER is not used.
• 100M MII mode, the ICS1893Y-10 asserts a signal on the RXER pin
when either of the following two conditions are true:
– Errors are detected during the reception of valid frames
– A False Carrier is detected
Note:
1. An ICS1893Y-10 asserts a signal on the RXER pin upon detection of a
False Carrier so that repeater applications can prevent the
propagation of a False Carrier.
2. The RXER signal always transitions synchronously with RXCLK.
3. The signal on RXER pin is conditioned by the RXTRI pin.
RXTRI
41
Input Receive (Interface), Tri-State.
The input on this pin is from a MAC. When the signal on this pin is logic:
• Low, the MAC indicates that it is not in a tri-state condition.
• High, the MAC indicates that it is in a tri-state condition. In this case,
the ICS1893Y-10 acts to ensure that only one PHY is active at a time.
TXCLK
43
Output Transmit Clock.
The ICS1893Y-10 generates this clock signal to synchronize the transfer
of data from the MAC/Repeater Interface to the ICS1893Y-10. When the
mode is:
• 10Base-T, the TXCLK frequency is 2.5 MHz.
• 100Base-TX, the TXCLK frequency is 25 MHz.
TXD0,
45,
Input Transmit Data 0–3.
TXD1,
46,
• TXD0 is the least-significant bit and TXD3 is the most-significant bit of
TXD2,
47,
TXD3
48
the MII transmit data nibble received from the MAC/repeater.
• The ICS1893Y-10 samples its TXEN signal to determine when data is
available for transmission. When TXEN is asserted, the signals on a
the TXD[3:0] pins are sampled synchronously on the rising edges of
the TXCLK signal.
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
113
January, 2004