ICS1893Y-10 Datasheet, PDF (116/150 Pages) –

ICS1893Y-10 Data Sheet - Release
Chapter 8 Pin Diagram, Listings, and Descriptions
Table 8-6. MAC/Repeater Interface Pins: 100M Symbol Interface (Continued)
MII Pin 100M Pin
Name Symbol No.
Pin
Name
Pin
Type
Pin Description
RXCLK SRCLK
38 Output (Symbol) Receive Clock.
In Symbol Mode, the ICS1893Y-10 sources an SRCLK to a
MAC/repeater. The SRCLK synchronizes the signals on the
SRD[4:0] pins between the ICS1893Y-10 and the
MAC/repeater. The following table contrasts the SRCLK
behavior when the mode for the ICS1893Y-10 is either
10Base-T or 100Base-TX.
10Base-T
100Base-TX
The SRCLK frequency is The SRCLK frequency is
2.5 MHz.
25 MHz.
The ICS1893Y-10
generates its SRCLK from
the MDI data stream using
a digital PLL. When the
MDI data stream
terminates the PLL
continues to operate,
synchronously referenced
to the last packet received.
The ICS1893Y-10
generates its SRCLK from
the MDI data stream while
there is a valid link (that is,
either data or IDLEs). In
the absence of a link, the
ICS1893Y-10 uses the
REF_IN clock to generate
the SRCLK.
The ICS1893Y-10
switches between clock
sources during the period
between when its SCRS is
asserted and prior to its
RXDV being asserted.
While the ICS1893Y-10 is
locking onto the incoming
data stream, a clock phase
change of up to 360
degrees can occur.
While the ICS1893Y-10 is
bringing up a link, a clock
phase change of up to 360
degrees can occur.
The RXCLK aligns once
per packet.
The RXCLK aligns once,
when the link is being
established.
Note: The signal on the SRCLK pin is conditioned by the
RXTRI pin.
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
116
January, 2004