ICS1893Y-10 Datasheet, PDF (126/150 Pages) –

ICS1893Y-10 Data Sheet - Release
Chapter 9 DC and AC Operating Conditions
9.5.2 Timing for Transmit Clock (TXCLK) Pins
Table 9-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various
interfaces. Figure 9-3 shows the timing diagram for the time periods.
Table 9-9. Transmit Clock Timing
Time
Period
Parameter
t1 TXCLK Duty Cycle
t2a TXCLK Period
t2b TXCLK Period
t2c TXCLK Period
t2d TXCLK Period
Conditions
Min. Typ. Max. Units
–
35 50 65 %
100M MII (100Base-TX)
– 40 – ns
10M MII (10Base-T)
– 400 – ns
100M Symbol Interface (100Base-TX) – 40 – ns
10M Serial Interface (10Base-T)
– 100 – ns
Figure 9-3. Transmit Clock Timing Diagram
t1
TXCLK
t2x
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
126
January, 2004