ICS1893Y-10 Datasheet, PDF (137/150 Pages) –

ICS1893Y-10 - Release
Chapter 9 DC and AC Operating Conditions
9.5.13 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
Table 9-20 lists the significant time periods for the 100M MII carrier assertion/de-assertion during
half-duplex transmission. The time periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• CRS
Figure 9-14 shows the timing diagram for the time periods.
Table 9-20. 100M MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Time
Period
Parameter
t1 TXEN Sampled Asserted to CRS Assert
t2 TXEN De-Asserted to CRS De-Asserted
Condi- Min.
tions
0
0
Typ.
3
3
Max. Units
4 Bit times
4 Bit times
Figure 9-14. 100M MII Carrier Assertion/De-Assertion Timing Diagram
(Half-Duplex Transmission Only)
t2
TXEN
TXCLK
CRS
t1
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
137
January, 2004