ICS1893Y-10 Datasheet, PDF (131/150 Pages) –

ICS1893Y-10 - Release
Chapter 9 DC and AC Operating Conditions
9.5.7 MII Management Interface Timing
Table 9-14 lists the significant time periods for the MII Management Interface timing (which consists of
timings of signals on the MDC and MDIO pins). Figure 9-8 shows the timing diagram for the time periods.
Table 9-14. MII Management Interface Timing
Time
Period
Parameter
t1 MDC Minimum High Time
t2 MDC Minimum Low Time
t3 MDC Period
t4 MDC Rise Time to MDIO Valid
t5 MDIO Setup Time to MDC
t6 MDIO Hold Time after MDC
Conditions Min. Typ. Max. Units
–
160 –
–
ns
–
160 –
–
ns
–
400† †
–
ns
–
0
– 300 ns
–
10
–
–
ns
–
10
–
–
ns
† The ICS1893Y-10 is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading
of MDC.
Figure 9-8. MII Management Interface Timing Diagram
MDC
MDIO
(Output)
t1
t2
t3
t4
MDC
MDIO
(Input)
t5
t6
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
131
January, 2004