ICS1893Y-10 Datasheet, PDF (102/150 Pages) –

ICS1893Y-10 Data Sheet - Release
Chapter 7 Management Register Set
7.14.5 Twisted Pair Tri-State Enable, TPTRI (bit 19.7)
The ICS1893Y-10 provides a Twisted Pair Tri-State Enable bit. This bit forces the TP_TXP and TP_TXN
signals to a high-impedance state. When this bit is set to logic:
• Zero, the Twisted Pair Interface is operational.
• One, the Twisted Pair Interface is tri-stated.
7.14.6 ICS Reserved (bits 19.6:1)
See Section 8.11.2, “ICS Reserved (bits 16.14:8)”, the text for which also applies here.
7.14.7 Automatic 100Base-TX Power-Down (bit 19.0)
The Automatic 100Base-TX Power Down bit provides an STA with the means of enabling the ICS1893Y-10
to automatically shut down 100Base-TX support functions when 10Base-T operations are being used.
When this bit is set to logic:
• Zero, the 100Base-TX Transceiver does not power down automatically in 100Base-TX mode.
• One, and the ICS1893Y-10 is operating in 10Base-T mode, the 100Base-TX Transceiver automatically
turns off to reduce the overall power consumption of the ICS1893Y-10.
Note: There are other means of powering down the 100Base-TX Transceiver (for example, when the
entire device is isolated using bit 0:10).
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
102
January, 2004