ICS1893Y-10 Datasheet, PDF (70/150 Pages) –

ICS1893Y-10 Data Sheet - Release
Chapter 7 Management Register Set
7.3.2 100Base-TX Full Duplex (bit 1.14)
The STA reads this bit to learn if the ICS1893Y-10 can support 100Base-TX, full-duplex operations. The
ISO/IEC specification requires that the ICS1893Y-10 must set bit 1.14 to logic:
• Zero if it cannot support 100Base-TX, full-duplex operations.
• One if it can support 100Base-TX, full-duplex operations. (For the ICS1893Y-10, the default value of bit
1.14 is logic one, in that the ICS1893Y-10 supports 100Base-TX, full-duplex operations.)
Bit 1.14 is a Command Override Write bit, which allows an STA to alter the default value of this bit. [See the
description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “Register 16: Extended
Control Register”.]
7.3.3 100Base-TX Half Duplex (bit 1.13)
The STA reads this bit to learn if the ICS1893Y-10 can support 100Base-TX, half-duplex operations. The
ISO/IEC specification requires that the ICS1893Y-10 must set bit 1.13 to logic:
• Zero if it cannot support 100Base-TX, half-duplex operations.
• One if it can support 100Base-TX, half-duplex operations. (For the ICS1893Y-10, the default value of bit
1.13 is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the
ICS1893Y-10 supports 100Base-TX, half-duplex operations.)
This bit 1.13 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “Register 16:
Extended Control Register”.]
7.3.4 10Base-T Full Duplex (bit 1.12)
The STA reads this bit to learn if the ICS1893Y-10 can support 10Base-T, full-duplex operations. The
ISO/IEC specification requires that the ICS1893Y-10 must set bit 1.12 to logic:
• Zero if it cannot support 10Base-T, full-duplex operations.
• One if it can support 10Base-T, full-duplex operations. (For the ICS1893Y-10, the default value of bit 1.12
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the
ICS1893Y-10 supports 10Base-T, full-duplex operations.)
This bit 1.12 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “Register 16:
Extended Control Register”.]
7.3.5 10Base-T Half Duplex (bit 1.11)
The STA reads this bit to learn if the ICS1893Y-10 can support 10Base-T, half-duplex operations. The
ISO/IEC specification requires that the ICS1893Y-10 must set bit 1.11 to logic:
• Zero if it cannot support 10Base-T, half-duplex operations.
• One if it can support 10Base-T, half-duplex operations. (For the ICS1893Y-10, the default value of bit
1.11 is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the
ICS1893Y-10 supports 10Base-T, half-duplex operations.)
Bit 1.11 of the ICS1893Y-10 Status Register is a Command Override Write bit., which allows an STA to alter
the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in
Section 7.11, “Register 16: Extended Control Register”.]
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
70
January, 2004