ICS1893Y-10 Datasheet, PDF (77/150 Pages) –

ICS1893Y-10 - Release
Chapter 7 Management Register Set
7.5.3 Revision Number (bits 3.3:0)
Table 7-10 lists the valid ICS1893Y-10 revision numbers, which are 4-bit binary numbers stored in bits
3.3:0.
Table 7-10. ICS1893Y-10 Revision Number
Decimal
1
Bits 3.3:0
0001
ICS First Release
Description
7.6 Register 4: Auto-Negotiation Register
Table 7-11 lists the bits for the Auto-Negotiation Register. An STA uses this register to select the
ICS1893Y-10 capabilities that it wants to advertise to its remote link partner. During the auto-negotiation
process, the ICS1893Y-10 advertises (that is, exchanges) capability data with its remote link partner by
using a pre-defined Link Code Word. The Link Code Word is embedded in the Fast Link Pulses exchanged
between PHYs when the ICS1893Y-10 has its Auto-Negotiation sublayer enabled. The value of the Link
Control Word is established based on the value of the bits in this register.
Note: For an explanation of acronyms used in Table 7-5, see Chapter 1, “Abbreviations and Acronyms”.
Table 7-11. Auto-Negotiation Advertisement Register (register 4 [0x04])
Bit
Definition
When Bit = 0
When Bit = 1
4.15 Next Page
Next page not supported Next page supported
4.14 IEEE reserved
Always 0
N/A
4.13 Remote fault
Locally, no faults detected Local fault detected
4.12 IEEE reserved
Always 0
N/A
4.11 IEEE reserved
Always 0
N/A
4.10 IEEE reserved
Always 0
N/A
4.9 100Base-T4
Always 0. (Not supported.) N/A
4.8 100Base-TX, full duplex Do not advertise ability
Advertise ability
4.7 100Base-TX, half duplex Do not advertise ability
Advertise ability
4.6 10Base-T, full duplex Do not advertise ability
Advertise ability
4.5 10Base-T half duplex Do not advertise ability
Advertise ability
4.4 Selector Field bit S4
IEEE 802.3-specified default N/A
4.3 Selector Field bit S3
IEEE 802.3-specified default N/A
4.2 Selector Field bit S2
IEEE 802.3-specified default N/A
4.1 Selector Field bit S1
IEEE 802.3-specified default N/A
4.0 Selector Field bit S0
N/A
IEEE 802.3-specified
default
Ac-
cess
R/W
CW
R/W
CW
CW
CW
CW
Note 1
Note 1
Note 1
Note 1
CW
CW
CW
CW
CW
SF De- Hex
fault
–0 0
– 0†
–0
– 0†
– 0† 1
– 0†
–0
–1
–1 E
–1
–1
–0
–0 1
–0
–0
–1
† As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
Note 1:
• In Hardware mode (that is, HW/SW pin is logic zero), this bit is a Read-Only bit.
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
77
January, 2004