ICS1893Y-10 Datasheet, PDF (110/150 Pages) –

ICS1893Y-10 Data Sheet - Release
Chapter 8 Pin Diagram, Listings, and Descriptions
Table 8-4. Configuration Pins (Continued)
Pin
Name
HW/SW
LOCK
Pin
Number
23
27
Pin
Type
Input
Output
Pin Description
Hardware/Software (Select).
When the signal on this pin is logic:
• Low, this pin selects Hardware mode operations.
• High, this pin selects Software mode operations.
(Stream Cipher) Lock (Acquired).
When the signal on this pin is logic:
• Low, the ICS1893Y-10 does not have a lock on the data stream.
• High, the ICS1893Y-10 has a lock on the data stream.
LSTA
21
Output Link Status.
This pin is used to report the status of the link segment. When the
signal on this pin is logic:
• Low, there is no link established.
• High, there is a link established.
This pin is mapped according to the interface for which the
ICS1893Y-10 is mapped. For the:
• Media Independent Interface (MII), the LSTA is mapped as LSTA.
• 100M Symbol Interface, the LSTA is mapped as SD.
• 10M Serial Interface, the LSTA is mapped as LSTA.
• Link Pulse Interface, the LSTA is mapped as SD.
MII/SI
19
Input Media Independent Interface / Stream Interface (Select).
This pin is used in combination with the 10/LP and 10/100SEL pins to
configure the ICS1893Y-10 MAC/Repeater Interface. When the signal
on this pin is logic:
• Low, this pin configures the MAC/Repeater Interface as a Media
Independent Interface.
• High, this pin configures the MAC/Repeater Interface as a Stream
Interface.
NOD/REP
1
Input
Node/Repeater (Select).
This selection on this pin affects both the SQE test and the Carrier
Sense (CSR) signal. When the signal on this pin is logic:
• Low, this pin enables the ICS1893Y-10 to default to node
operations.
• High, this pin enables the ICS1893Y-10 to default to repeater
operations.
REF_IN
53
Input (Frequency) Reference Input.
This pin is connected to a 25-MHz oscillator or crystal. For a tolerance,
see Section 9.5.1, “Timing for Clock Reference In (REF_IN) Pin”.
REF_OUT
52
Input (Frequency) Reference Output.
This pin is used with a crystal.
RESETn
18
Input (System) Reset (Active Low).
• When the signal on this active-low pin is logic:
– Low, the ICS1893Y-10 is in hardware reset.
– High, the ICS1893Y-10 is operational.
• For more information on hardware resets, see the following:
– Section 4.1.2.1, “Hardware Reset”
– Section 9.5.18, “Reset: Hardware Reset and Power-Down”
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
110
January, 2004