HD404669 Datasheet, PDF (85/142 Pages) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

HD404669 Series
State
Transfer completion
(IFS1← 1)
Interrupts inhibited
IFS1^← 0
SM1A write
Yes
IFS1 = 1?
Transmit clock
error processing
No
Normal
termination
Transmit clock error detection flowchart
Transmit clock
wait state
Transfer state
Transmit clock wait state
Transfer state
SCK₁ pin (input)
Noise
SM1A write
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit clock
error. When SM1A is written,
IFS1 is set.
IFS1
Flag set because octal
counter reaches 000
Flag reset at
transfer completion
Transmit clock error detection procedure
Figure 61 Transmit Clock Error Detection
85