HD404669 Datasheet, PDF (84/142 Pages) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

HD404669 Series
Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 61. If more than eight transmit clocks are input
in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the
serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and transmit clock wait state is entered. At the
falling edge of the next normal clock signal, the transfer state is entered.
Meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial 1 interrupt
request flag is reset, and a dummy write is performed to serial mode register 1A (SM1A: $005). The serial
interface then returns to the STS wait state, and the serial 1 interrupt request flag (IFS1: $003, 2) is set
again. It is therefore possible to detect a serial clock error by testing the serial 1 interrupt request flag after
the dummy write to serial mode register 1A.
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