HD404669 Datasheet, PDF (46/142 Pages) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

HD404669 Series
Input control signal
Input data
V_CC
Buffer control signal
DCD
Pull-down MOS
Output data
PDR
Pull-down MOS
control signal
MIS3
HLT
Figure 28 I/O Buffer Configuration (with Pull-Down MOS)
Table 14 I/O Pin Control by Register Settings (with Pull-Up MOS)
MIS3 (bit 3 of MIS)
0
1
DCD, DCR
0
1
0
1
PDR
0
1
0
1
0
1
0
1
CMOS buffer PMOS
—
—
—
On
—
—
—
On
NMOS
—
—
On
—
—
—
On
—
Pull-up MOS
—
—
—
—
—
On
—
On
Note: 1. — indicates off status.
2. PDR is not assigned to a RAM address. It is accessed with special input/output instructions.
Table 15 I/O Pin Control by Register Settings (with Pull-Down MOS)
MIS3 (bit 3 of MIS)
0
1
DCD
0
1
0
1
PDR
0
1
0
1
0
1
0
1
CMOS buffer PMOS
—
—
—
On
—
—
—
On
NMOS
—
—
On
—
—
—
On
—
Pull-down
MOS
—
—
—
—
On
—
On
—
Note: 1. — indicates off status.
2. PDR is not assigned to a RAM address. It is accessed with special input/output instructions.
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