HD404669 Datasheet, PDF (41/142 Pages) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

HD404669 Series
Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 23. As shown in table 13, a ceramic
oscillator or crystal oscillator can be connected to OSC₁ and OSC₂, and a 32.768-kHz oscillator can be
connected to X1 and X2. The system oscillator can also be operated by an external clock. Set bits 0 and 1
(SSR10, SSR11) of system clock select register 1 (SSR1: $029) and bits 2 and 3 (SSR22, SSR23) of system
clock select register 2 (SSR2: $02A) according to the frequency of the oscillator connected to OSC₁ and
OSC₂ (figures 24 and 25).
The system clock division ratio can be set with bits 0 and 1 (SSR20, SSR21) of system clock select register
2 (SSR2: $02A). The value set in these bits does not become valid until watch mode is entered. Therefore,
the system clock must be halted temporarily when changing the division ratio.
The system clock division ratio immediately after a reset or when stop mode is cleared can be selected by
means of the SEL pin level, division-by-4 being selected when the SEL pin is at Vcc potential, and
division-by-32 when at GND potential.
Note: If the system clock select register 1 and 2 (SSR1, SSR2: $029, $02A) setting does not match the
oscillator frequency, DTMF generation circuit and subsystems using the 32.768-kHz oscillation
will malfunction.
LSON
OSC₂
OSC₁
X1
X2
System ^fOSC 1/4, 1/8, ^fcyc
clock
oscillator
1/16 or
1/32
t_cyc
division
circuit
Timing
generation
circuit
Sub-
system
f_X
f_SUB
1/8 or 1/4
Timing
division ^tsubcyc generation
clock
circuit
circuit
oscillator
ø_CPU
System
clock
selection
circuit
ø_PER
CPU with ROM,
RAM, registers,
flags, and I/O
Internal
Peripheral
module
interrupts
TMA3 bit
1/8
division
circuit
f_W
t_Wcyc
Timing
generation
circuit
Time-base
clock øCLK
selection
circuit
Time base
interrupt
Figure 23 Clock Generation Circuit
41