HD404669 Datasheet, PDF(12/142 Page) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

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HD404669 Datasheet, PDF (12/142 Pages) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

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HD404669 Series

RAM address

$000

RAM-mapped register area

$040

$050

Memory registers

(16 digits)

Not used

$090

$260

$2F0

$3C0

$3FF

Data (464 digits x 2)

V = 0 (bank = 0)

V = 1 (bank = 1)

Data (144 digits)

Not used

Stack area (64 digits)

R : Read only

W : Write only

R/W : Read/Write

Note : *1. There are two data areas, V = 0 (bank 0) and

V = 1 (bank 1)

$090

Data

(464 digits)

V=0

(bank = 0)

Data

(464 digits)

V=1

(bank = 1)

$25F

RAM address

$000

$001

$002

Interrupt control bit area

$003

$004 Port mode register A

(PMRA) W

$005 Serial mode register 1A

(SM1A) W

$006 Serial data register 1L

(SR1L) R/W

$007 Serial data register 1U

(SR1U) R/W

$008 Timer mode register A

(TMA) W

$009

$00A

$00B

Not used

$00C Miscellaneous register

(MIS) W

$00D Timer mode register C1

(TMC1) W

$00E Timer C

$00F

(TRCL/TWCL) R/W

(TRCU/TWCU) R/W

$010 Timer mode register D1

(TMD1) W

$011 Timer D

$012

(TRDL/TWDL) R/W

(TRDU/TWDU) R/W

$013

Not used

$014 Timer mode register C2

(TMC2) R/W

$015 Timer mode register D2

(TMD2) R/W

$016

Not used

$017 Compare data register

(CDR) R

$018 Compare enable register

(CER) W

$019 Tone generator mode register

(TGM) W

$01A Tone generator control register

(TGC) W

$01B

$01C

$01D

Not used

$01E

$01F

$020

$021

$022

$023

$024

$025

$026

$027

$028

$029

$02A

$02B

$02C

$02D

$02E

$02F

$030

$031

$032

$033

$034

$035

Port mode register B

Port mode register C

Detection edge select register 1

Detection edge select register 2

Serial mode register 1B

System clock select register 1

System clock select register 2

Not used

Data control register D0 to D3

Data control register D4 to D5

Data control register D9 to D11

Not used

Data control register R0

Data control register R1

Data control register R2

Data control register R3

Data control register R4

Not used

(PMRB) W

(PMRC) W

(ESR1) W

(ESR2) W

(SM1B) W

(SSR1) W

(SSR2) W

(DCD0) W

(DCD1) W

(DCD2) W

(DCR0) W

(DCR1) W

(DCR2) W

(DCR3) W

(DCR4) W

$036

$037

$038

$039

$03A

$03B

Data control register R6

Data control register R7

Data control register R8

Data control register R9

Data control register RA

(DCR6) W

(DCR7) W

(DCR8) W

(DCR9) W

(DCRA) W

$03C

$03D

Not used

$03E

$03F V register

(V) R/W

*2. Two registers are mapped onto the same address ($00E, $00F, $011, $012)

$00E Timer read register CL

$00F Timer read register CU

(TRCL) R Timer write register CL

(TRCU) R Timer write register CU

(TWCL) W

(TWCU) W

$011 Timer read register DL

$012 Timer read register DU

(TRDL) R Timer write register DL

(TRDU) R Timer write register DU

(TWDL) W

(TWDU) W

Figure 2 RAM Memory Map

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