HD404669 Datasheet, PDF (55/142 Pages) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

HD404669 Series
Pull-up and Pull-down MOS Transistor Control
The D₄, D₅, D₉ to D₁₁, and the R port pins have built-in pull-up MOS transistors that can be controlled by
software, and the D₀ to D₃ pins have built-in pull-down MOS transistors that can be controlled by software.
The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS:
$00C), and the on/off status of an individual transistor can also be controlled by the port data register
(PDR) of the corresponding pin—enabling on/off control of that pin alone (tables 14, 15 and figure 37).
The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
Miscellaneous register (MIS: $00C)
Bit
Initial value
Read/Write
Bit name
3
0
W
MIS3
2
0
W
MIS2
1
0
W
MIS1
0
0
W
MIS0
MIS3
0
1
Pull-up/Pull-down
MOS transistor
control
Off
Active
MIS2
0
1
CMOS buffer
on/off selection
for pin R4₃/SO₁
Active
Off
MIS1
MIS0
t_RC selection.
Refer to figure 18 in the
operation modes section.
Figure 37 Miscellaneous Register (MIS)
How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to V_CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to V_CC by
their pull-up MOS transistors or by resistors of about 100 kΩ. Pins provided with pull-down MOS should
be pulled down to GND potential with the built-in pull-down MOS or connected to GND.
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