HD404669 Datasheet, PDF (29/142 Pages) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

HD404669 Series
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.
Table 7 Timer A, C, D Interrupt Request Flags
(IFTA: $001, Bit 2, IFTC: $002, Bit 2, IFTD: $003, Bit 0)
Timer A, C, D Interrupt
Request Flags (IFTA,
IFTC, IFTD)
0
1
Interrupt Request
No
Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the
timer A interrupt request flag, as listed in table 8.
Table 8 Timer A, C, D Interrupt Masks (IMTA: $001, Bit 3, IMTC: $002, Bit 3, IMTD: $003, Bit 1)
Timer A, C, D Interrupt
Masks (IMTA, IMTC,
IMTD)
0
1
Interrupt Request
Enabled
Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 7.
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as listed in table 8.
Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the
rising or falling of signals input to EVND when the input capture function is used, as listed in table 7.
Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 8.
Serial 1 Interrupt Request Flag (IFS1: $003, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 9.
Table 9 Serial 1 Interrupt Request Flag (IFS1: $003, Bit 2)
IFS1
0
1
Interrupt Request
No
Yes
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