HD404669 Datasheet, PDF (69/142 Pages) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

EVND
Edge detection
logic
Input capture
status flag
(ICSF)
Input capture
error flag
(ICEF)
Error control
logic
Read signal
HD404669 Series
Timer D
interrupt
request flag
(IFTD)
System
clock
ø _PER
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
Timer read register D
(TRDL)
(TRDU)
4
4
clock
Timer counter D
(TCDL)
(TCDU)
Input capture timer control
3
Timer mode
register D1
(TMD1)
2
Timer mode
register D2
(TMD2)
Edge detection
select register 2
Edge detection control
(ESR2)
Data bus
Clock line
Signal line
Figure 49(2) Block Diagram of Timer D (Input Capture Timer)
69