HD404669 Datasheet, PDF (14/142 Pages) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

HD404669 Series
Bits in the interrupt control bits area and register flag area can be set and reset by the
SEM or SEMD instruction and the REM or REMD instruction, and tested by the TM or
TMD instruction. They are not affected by any other instructions.
The following restrictions apply to individual bits.
SEM/SEMD
REM/REMD
TM/TMD
IE
IM
LSON
IF
ICSF
ICEF
RAME
RSP
WDON
DTON
Allowed
Allowed
Not executed
Allowed
Not executed
Allowed
Not executed in active mode
Used in subactive mode
Allowed
Not executed
Allowed
Allowed
Allowed
Inhibited
Inhibited
Allowed
Not used
Not executed
Not executed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
14