HD404669 Datasheet, PDF (25/142 Pages) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

HD404669 Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt
Cuntrol Bit INT₀
INT₁
Timer A INT₂
Timer C
or INT₃
Timer D
or INT₄
IE
1
1
1
1
1
1
IF0 ^. IM0
1
0
0
0
0
0
IF1 ^. IM1
*
1
0
0
0
0
IFTA ^. IMTA *
*
1
0
0
0
IF2 ^. IM2
*
*
*
1
0
0
IFTC ^. IMTC *
*
*
*
1
0
+ IF3 ^. IM3
IFTD ^. IMTD *
*
*
*
*
1
+ IF4 ^. IM4
IFS1 ^. IMS₁ *
*
*
*
*
*
Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.
Serial 1
1
0
0
0
0
0
0
1
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a 2-cycle instruction.
Figure 10 Interrupt Sequence
Execution of
instruction at
start address
of interrupt
routine
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