HD404669 Datasheet, PDF(23/142 Page) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

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HD404669 Datasheet, PDF (23/142 Pages) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

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HD404669 Series

Interrupts

The MCU has 9 interrupt sources: five external signals (INT0, INT1, INT2âINT4), three timer/ counters

(timers A, C, and D), serial interface (Serial 1).

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt

source, and an interrupt enable flag (IE) controls the entire interrupt process.

As vector addresses are shared by interrupt sources timer C and INT3, and timer D and INT4, so the type of

request that has occurred must be checked at the beginning of interrupt processing.

Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are

reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag

(IE) and the IF to 0 and the interrupt mask (IM) to 1.

A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector

addresses are listed in table 2, and interrupt processing conditions for the 9 interrupt sources are listed in

table 3.

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the

interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to

that interrupt source.

The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in

figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The

IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack

during the second and third cycles, and the program jumps to the vector address to execute the instruction

in the third cycle.

Program the JMPL instruction at each vector address, to branch the program to the start address of the

interrupt program, and reset the IF by a software instruction within the interrupt program.

Table 2 Vector Addresses and Interrupt Priorities

Reset/Interrupt

Priority

Vector Address

RESET, STOPC*

$0000

INT0

INT1

Timer A

$0002

$0004

$0006

INT2

$0008

Timer C, INT3

$000A

Timer D, INT4

$000C

Serial 1

$000E

Note: * The STOPC interrupt request is valid only in stop mode.

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