HD404669 Datasheet, PDF (81/142 Pages) Hitachi Semiconductor – Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

External clock mode
STS wait state
(Octal counter 1 = 000,
transmit clock disabled)
HD404669 Series
00 MCU reset
SM1A write 04
01 STS instruction
06 SM1A write (IFS1^← 1)
Transmit clock wait state
(Octal counter 1 = 000)
02 Transmit clock
03
8 transmit clocks
05
STS instruction (IFS1^← 1)
Transfer state
(Octal counter 1 = 000)
Internal clock mode
SM1A write
18
STS wait state
(Octal counter 1 = 000,
transmit clock disabled)
10 MCU reset
Continuous clock output state
(PMRA 0, 1 = 00)
SM1A write 14
11 STS instruction
Transmit clock 17
Transmit clock wait state
(Octal counter 1 = 000)
12 Transmit clock
15
STS instruction (IFS1← 1)
13 8 transmit clocks
16 SM1A write (IFS1← 1)
Transfer state
(Octal counter 1 = 000)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 59 Serial Interface State Transitions
• Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge
of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments
the octal counter, shifts the serial data register 1 (SR1L: $006, SR1U: $007), and enters the serial
interface in transfer state. However, note that if continuous clock output mode is selected in internal
clock mode, the serial interface does not enter transfer state but enters continuous clock output state
(17).
The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04,
14) in transmit clock wait state.
• Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the
eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the
octal counter to 000, and the serial interface enters another state. When the STS instruction is executed
(05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is
entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.
In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes the serial
interface, and STS wait state is entered.
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