MB86293 Datasheet, PDF (8/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

10.2.4 Drawing control registers ..................................................................................... 199
10.2.5 Drawing mode registers........................................................................................ 202
10.2.6 Triangle drawing registers .................................................................................... 220
10.2.7 Line drawing registers.......................................................................................... 223
10.2.8 Pixel drawing registers ......................................................................................... 224
10.2.9 Rectangle drawing registers.................................................................................. 224
10.2.10 Blt registers ...................................................................................................... 225
10.2.11 High-speed 2D line drawing registers ................................................................ 226
10.2.12 High-speed 2D triangle drawing registers.......................................................... 227
10.2.13 Geometry control register.................................................................................. 228
10.2.14 Geometry mode registers................................................................................... 230
10.2.15 Display list FIFO registers ................................................................................ 237
11 TIMING DIAGRAM .............................................................................................................. 238
11.1 HOST INTERFACE .................................................................................................... 238
11.1.1 CPU read/write timing diagram in SH3 mode (Normally Not Ready Mode)........... 238
11.1.2 CPU read/write timing diagram in SH3 mode (Normally Ready Mode) ................. 239
11.1.3 CPU read/write timing diagram in SH4 mode (Normally Not Ready Mode)........... 240
11.1.4 CPU read/write timing diagram in SH4 mode (Normally Ready Mode) ................. 241
11.1.5 CPU read/write timing diagram in V832 mode (Normally Not Ready Mode) ......... 242
11.1.6 CPU read/write timing diagram in V832 mode (Normally Ready Mode) ................ 243
11.1.7 CPU read/write timing diagram in SPARClite (Normally Not Ready Mode) .......... 244
11.1.8 CPU read/write timing diagram in SPARClite (Normally Ready Mode)................. 245
11.1.9 SH4 single-address DMA write (transfer of 1 long word)....................................... 246
11.1.10 SH4 single-address DMA write (transfer of 8 long words) .................................. 247
11.1.11 SH3/4 dual-address DMA (transfer of 1 long word) ............................................ 248
11.1.12 SH3/4 dual-address DMA (transfer of 8 long words)........................................... 248
11.1.13 V832 DMA transfer ........................................................................................... 249
11.1.14 SH4 single-address DMA transfer end timing .................................................... 250
11.1.15 SH3/4 dual-address DMA transfer end timing ................................................... 250
11.1.16 V832 DMA transfer end timing.......................................................................... 251
11.1.17 SH4 dual DMA write without ACK .................................................................... 252
11.1.18 Dual-address DMA (without ACK) end timing ................................................... 253
11.2 GRAPHICS MEMORY INTERFACE ........................................................................................ 254
11.2.1 Timing of read access to same row address ........................................................... 254
11.2.2 Timing of read access to different row addresses................................................... 255
11.2.3 Timing of write access to same row address .......................................................... 256
11.2.4 Timing of write access to different row addresses.................................................. 257
11.2.5 Timing of read/write access to same row address .................................................. 258
11.2.6 Delay between ACTV commands........................................................................... 259