MB86293 Datasheet, PDF (63/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
6.6 T h e e x t e r n a l s y n c h r o n o u s s i g n a l
The display scan can be performed by synchronizing horizontal/vertical synchronous signal from the
external.
In selecting the external synchronization mode, Coral is sampling the HSYNC signal and displays
the synchronizing the external video signal. Either the internal PLL clock or the DCLKI input
signal could be selected for the sampling clock. Also, the superimposed analog output is performed
by the chroma key process. The following diagram shows an example of the external
synchronization circuit.
External Sync
Enable
Hsync In
Vsync In
3 states
buffer
Hsync Out
Vsync Out
HSYNC
VSYNC
ESY bit
Display Timming
Generator
L0
L1
L2
L3
L0
L4
L5
Cursor 0
Cursor 1
CKM bit
CORAL
KEYC
register
Compare
GV
Latency compensation for DAC D-FFs
Digital
RGB
Out
Analo g
RGB In
Video SW
(Pedestal Clump Input)
Superimposed
Analog
RGB Out
An example of the external synchronization circuit
The external synchronization mode is performed by setting the ESY bit of the DCM register. In
setting the external synchronization mode, HSYNC, VSYNC, and EO pin of Coral is changed to the
input mode. After that it needs to be provided the synchronous signal by using the 3 state buffer from
the external. When turning off the external synchronization mode, Coral internal ESY bit needs to be
switched OFF after disconnecting the synchronous input signal from the external.
The buffer of the external synchronization signal must not be switched ON when the synchronous
output signal of Coral is ON. Follow the previous instruction to prevent simultaneous ON from
occurring.
In using the external synchronous signal with the display clock based on the internal PLL, Coral
extends the clock period and fits the clock phase with the horizontal synchronous signal phase after
inputting the horizontal synchronous pulse. The following caution is necessary. In case of
connecting the high speed transmit signal, such as LVDS, with the digital RGB output, PLL with a
built-in the high speed serial transmission is temporally unstable due to this connection. Therefore,
MB86293 CORAL_LQ
Graphics Controller
63
Specifications Rev. 1.1