MB86293 Datasheet, PDF (34/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
2.3.4 Clock input
Table 2-4 Clock Input Pins
Pin name
CLK
S
CKM
CLKSEL [1:0]
I/O
Input
Input
Input
Input
Description
Clock input signal
PLL reset signal
Clock mode signal
Clock rate select signal
Inputs source clock for internal operation clock and display dot clock. Normally, 4 Fsc (= 14.31818 MHz:
NTSC) is input. An internal PLL generates the internal operation clock of 166 MHz/133 MHz and the
display base clock of 400 MHz.
CKM
L
H
Clock mode
Output from internal PLL selected
Host CPU bus clock (BCLK1) selected
• When CKM = L, selects input clock frequency when built-in PLL used according to setting of CLKSEL pins
CLKSEL1
L
L
H
H
CLKSEL0
L
H
L
H
Input clock
frequency
Multiplication
rate
Inputs 13.5-MHz × 29
clock frequency
Inputs 14.32-MHz × 28
clock frequency
Inputs 17.73-MHz × 22
clock frequency
Reserved
Display
reference clock
391.5 MHz
400.96 MHz
390.06 MHz
MB86293 CORAL_LQ
Graphics Controller
34
Specifications Rev. 1.1