MB86293 Datasheet, PDF (144/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
IMASK (Interrupt MASK)
Register
address
HostBaseAddress + 24H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
Resv
Reserved
IMASK IMASK
R/W
R0
R 0W 0
R0
RW RW
Initial value
0
0
0
0
0
This register masks interrupt requests. Even when the interrupt request is issued for the bit to which
“0” is written, interrupt signal is not asserted for CPU.
Bit 0
CERRM (Command Error Interrupt Mask)
Masks drawing command execution error interrupt
Bit 1
CENDM (Command Interrupt Mask)
Masks drawing command end interrupt
Bit 2
VSYNCM (Vertical Sync. Interrupt Mask)
Masks vertical synchronization interrupt
Bit 3
FSYNCH (Frame Sync. Interrupt Mask)
Masks frame synchronization interrupt
Bit 4
SYNCERRM (Sync Error Mask)
Masks external synchronization error interrupt
SRST (Software ReSeT)
Register
address
HostBaseAddress + 2CH
Bit number
7
6
5
4
3
Bit field name
Reserved
R/W
R0
Initial value
0
2
1
0
SRST
W1
0
This register controls software reset. When “1” is set to this register, a software reset is performed.
MB86293 CORAL_LQ
Graphics Controller
144
Specifications Rev. 1.1