MB86293 Datasheet, PDF (142/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
DRM (DMA Request Mask)
Register
address
HostBaseAddress + 05H
Bit number
7
6
5
4
3
Bit field name
Reserved
R/W
R0
Initial value
0
2
1
0
DRM
RW
0
This register enables the DMA request. Setting “1” to this register to temporarily stop the DMA
request from the CORAL. The external request is enabled by setting “0” to this register.
DST (DMA STatus)
Register
address
HostBaseAddress + 06H
Bit number
7
6
5
4
3
Bit field name
Reserved
R/W
R0
Initial value
0
2
1
0
DST
R
0
This register indicates the DMA transfer status. DST is set to “1” during DMA transfer. This state is
cleared to “0” when the DMA transfer is completed.
DTS (DMA Transfer Stop)
Register
address
HostBaseAddress + 08H
Bit number
7
6
5
4
3
Bit field name
Reserved
R/W
R0
Initial value
0
2
1
0
DTS
RW
0
This register suspends DMA transfer.
An ongoing DMA transfer is suspended by setting DTS to “1”.
In the dual-address without ACK mode, to end the DMA transfer, write “1” to this register after CPU
DMA transfer.
LTS (display Transfer Stop)
Register
address
HostBaseAddress + 09H
Bit number
7
6
5
4
3
Bit field name
Reserved
R/W
R0
Initial value
0
This register suspends DisplayList transfer.
Ongoing DisplayList transfer is suspended by setting LTS to “1”.
2
1
0
LTS
RW
0
LSTA (displayList transfer STAtus)
Register
address
HostBaseAddress + 10H
Bit number
7
6
5
4
3
Bit field name
R/W
Reserved
R0
Initial value
0
2
1
0
LSTA
R
0
This register indicates the DisplayList transfer status from Graphics Memory. LSTA is set to “1” while
DisplayList transfer is in progress. This status is cleared to 0 when DisplayList transfer is completed
MB86293 CORAL_LQ
Graphics Controller
142
Specifications Rev. 1.1