MB86293 Datasheet, PDF (247/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
11.1.10 SH4 single-address DMA write (transfer of 8 long words)
BCLKIN
D[31:0]
DREQ
DRACK
Acceptance
DTACK
Bus cycle
CPU
DMAC
Acceptance
CPU
¡: DREQ sampling and channel priority determination for SH mode (DREQ = level detection)
Fig. 10.10 SH4 Single-address DMA Write (Transfer of 8 Long Words)
After the CPU has asserted DRACK, CORAL negates DREQ and receives 32-byte data in line with the
DTACK assertion timing. As soon as the next data is ready to be received, CORAL reasserts DREQ
but the reassertion timing depends on the internal status.
MB86293 CORAL_LQ
Graphics Controller
247
Specifications Rev. 1.1