MB86293 Datasheet, PDF (245/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
11.1.8 CPU read/write timing diagram in SPARClite (Normally Ready Mode)
( MODE[2:0]=011, RDY_MODE=1, BS_MODE=0)
T1 Tsw1 Tsw1 T2 T1 Tsw1 Tsw1 Thw1 Thw2 T2
CLKINI
ADR[23:2]
CS#
AS#
RDWR#
Hi-Z
D[31:0]
RDWR#
Valid Data
Hi-Z
Valid Data
BE#[3:0]
D[31:0]
Valid Data IN
Valid Data IN
READY#
Hi-Z
Hi-Z
Hi-Z
SoftWaiit SoftWait Ready
SoftWait HardWait HardWait HardWait Ready
¡: READY# sampling in SPARClite
×: Soft Wait (1 cycle) in SPARClite
T1: Read/write start cycle (READY# in ready state)
Tsw*: Software wait insertion cycle (2-cycle setting required)
Twh*: Hardware wait insertion cycle (READY# asserts Ready after the preparations)
T2: Read/write end cycle (READY# ends in ready state)
Note: BE# signal is used only for a write from the CPU; it is not used for a read from the CPU.
Fig. 10.8 Read/Write Timing Diagram in SPARClite (Normally Ready Mode)
MB86293 CORAL_LQ
Graphics Controller
245
Specifications Rev. 1.1