MB86293 Datasheet, PDF (243/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
11.1.6 CPU read/write timing diagram in V832 mode (Normally Ready
Mode)
( MODE[2:0]=010, RDY_MODE=1, BS_MODE=0)
T1 Tsw1 Tsw2 T2 T1 Tsw1 Tsw2 Thw1 Thw2 T2
BCLKI
A[23:2]
XCS
XBCYST
XMRD(XIORD)
D[31:0]
Hi-Z
XMWR(XIOWR)
XXXBEN[3:0])
Valid Data
OUT
Hi-Z
Valid Data
OUT
D[31:0]
XREADY
Hi-Z
Valid Data IN
Valid Data IN
Hi-Z
SoftWaiit SoftWait Ready
SoftWait SoftWait HardWait HardWait Ready
¡: XREADY sampling in V832 mode
×: Soft Wait (2 cycles) in V832 mode
T1: Read/write start cycle (XREADY in ready state)
Tsw*: Software wait insertion cycle (2-cycle setting required)
Twh*: Hardware wait insertion cycle (XREADY asserts Ready after the preparations)
T2: Read/write end cycle (XREADY ends in ready state)
Notes: 1.The XxxBEN signal is used only for a write from the CPU; it is not used for a read from the
CPU.
2.The CPU always inserts one cycle wait after read access.
Fig. 10.6 Read/Write Timing Diagram in V832 Mode (Normally Ready Mode)
MB86293 CORAL_LQ
Graphics Controller
243
Specifications Rev. 1.1