MB86293 Datasheet, PDF (40/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
4.3 D M A T r a n s f e r
4.3.1 Data transfer unit
DMA transfer is performed in double-word (32 bits) units or 8 double-word (32 bytes) units. Byte and
word access is not supported.
Note: 8 double-word transfer is supported only in the SH4 mode.
4.3.2 Address mode
Dual address mode (mode using ACK)
DMA is performed at memory-to-memory transfer between host memory and registers mapped in
memory space or graphics memory (destination). Both the host memory address and CORAL is used.
In the SH4 mode, the 1 double-word transfer (32 bits) and 8 double-word transfer (32 bytes) can be
used.
When the CPU transfer destination address is fixed, data can also be transferred to the FIFO interface.
However, in this case, even the SH4 mode supports only the 1 double-word transfer.
DREQ and DRACK pins and SRAM interface signals are used. In V832, the DREQ, DMAAK, and
XTC pins and SRAM interface signals are used.
Note: The SH3 mode supports the direct address mode; it does not support the indirect address
mode.
Dual address mode (mode not using ACK)
When not using the ACK signal with the dual address mode established, set bit3 at HostBase+0004h
(DNA: Dual address No Ack mode) to 1.
When the ACK is not used, the DREQ signal is in the edge mode and the DREQ signal is negated per
transfer and then reasserted it in the next cycle. If processing cannot be performed immediately
inside CORAL, the DREQ signal remains negated.
The transfer count register (DTC) of CORAL is not used, so in order to end DMA transfer, write “1” to
the DMA transfer stop register (DTS) from the CPU.
Note 1: In the dual DMA mode (mode without ACK), the destination address can be used only for the
FIFO.
In DMA transfer to the graphics memory, etc., use the dual DMA mode.
Note 2: DMA read is not supported.
Single address mode (FIFO interface)
Data is transferred between host memory (source) and FIFO (destination). Only the address output
from the host memory is used, and the data is transferred to the FIFO. This mode does not support
data write to the host memory. When the FIFO is full, the DMA transfer is suspended.
The 1 double-word transfer (32 bits) and the 8 double-word transfer (32 B) can be used.
DREQ, DTACK, and DRACK signal are used.
Note: The single-address mode is supported only in the SH4 mode.
MB86293 CORAL_LQ
Graphics Controller
40
Specifications Rev. 1.1