MB86293 Datasheet, PDF (252/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
11.1.17 SH4 dual DMA write without ACK
1234
CLK
/DREQ
/BS
/RD
/WE[3:0]
ADDRESS
/CS(CORAL)
Right to use bus
CPU
SAR
DAR
DMAC
When CORAL can not receive
data immediately, DREQ
negation continues.
While DREQ is issued at each
write access to CORAL, DREQ
is negated at every four
cycles..
Fig. 10.17 DREQ Negate Timing for Each Transfer
At each DMA transfer, DREQ is negated and then reasserted at the next cycle.
Only the FIFO address can be used as the destination address.
When CORAL cannot receive data immediately, DREQ negation continues. At that time, the negate
timing is not only above diagram.
MB86293 CORAL_LQ
Graphics Controller
252
Specifications Rev. 1.1