MB86293 Datasheet, PDF (143/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
DRQ (DMA ReQquest)
Register
address
HostBaseAddress + 18H
Bit number
7
6
5
4
3
Bit field name
Reserved
R/W
R0
Initial value
0
2
1
0
DRQ
RW1
0
This register starts sending external DMA request.
DMA transfer using the external request handshake is triggered by setting DRQ to “1”. The external
DREQ signal cannot be issued when DMA is masked by the DRM register. This register cannot be
written “0”. When DMA transfer is completed, this status is cleared to “0”.
IST (Interrupt STatus)
Register
address
HostBaseAddress + 20H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
Resv
Reserved
IST IST
R/W
R0
R0W0
R0
RW0 RW0
Initial value
0
0
0
0
0
This register indicates the current interrupt status. It shows that an interrupt request is issued when
“1” is set to this register. The interrupt status is cleared by writing “0” to this register.
Bit 0
Bit 1
CERR (Command Error Flag)
Indicates drawing command execution error interrupt
CEND (Command END)
Indicates drawing command end interrupt
Bit 2
Bit 3
Bit 4
Bit 17 and 16
VSYNC (Vertical Sync.)
Indicates vertical interrupt synchronization
FSYNC (Frame Sync.)
Indicates frame synchronization interrupt
SYNCERR (Sync. Error)
Indicates external synchronization error interrupt
Reserved
This field is provided for testing.
Normally, the read value is “0”, but note that it may be “1” when a drawing command
error (Bit 0) has occurred.
MB86293 CORAL_LQ
Graphics Controller
143
Specifications Rev. 1.1