MB86293 Datasheet, PDF (32/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
2.3.2 Video output interface
Pin name
DCLKO
DCLKI
HSYNC
VSYNC
CSYNC
DISPE
GV
R2-7
G2-7
B2-7
XRGBEN
Table 2-2 Video Output Interface Pins
I/O
Output
Input
I/O
I/O
Output
Output
Output
Output
Output
Output
Input
Description
Dot clock signal for display
Dot clock signal input
Horizontal sync signal output
Horizontal sync input <in external sync mode>
Vertical sync signal output
Vertical sync input <in external sync mode>
Composite sync signal output
Display enable period signal
Graphics/video switch
Digital picture (R) output
Digital picture (G) output
Digital picture (B) output
Signal to switch between RGB1 and 0 output/memory bus
(MD 63 to 58)
6-bit display data is output as standard for R, G, and B. Depending on the condition, 8-bit display data
can also be output for R, G, and B. Fixing XRGBEN at 0, R0, 1, G0, 1, and B0, 1 can be output to MD62,
63, MD60, 61, and MD58, 59 respectively. When 8-bit output is selected for R, G, and B, only the 32-bit
mode can be used for the memory bus width mode.
Additional setting of external circuits can generate composite video signal.
Synchronous to external video signal display can be performed.
Either mode which is synchronous to DCLKI signal or one which is synchronous to dot clock, as for
normal display can be selected.
Since HSYNC and VSYNC signals are set to input state after reset, these signals must be pulled up LSI
externally.
The GV signal switches graphics and video at chroma key operation. When video is selected, the “Low”
level is output.
MB86293 CORAL_LQ
Graphics Controller
32
Specifications Rev. 1.1