MB86293 Datasheet, PDF (41/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
4.3.3 Bus mode
Coral supports the DMA transfer cycle steal mode and burst mode according to setting of external DMA
mode.
Cycle steal mode (In the V832 mode, the burst mode is called the single transfer mode.)
In the cycle steal mode, the right to use the bus is obtained or released at every data transfer of 1 unit.
The DMA transfer unit can be selected from between the 1 double-word (32 bits) and 8 double-words
(32 B).
Burst mode (In the V832 mode, the burst mode is called the demand transfer mode.)
When DMA transfer is started, the right to use the bus is acquired and the transfer begins. The data
transfer unit can be selected from between the 1 double-word (32 bits) and 8 double-words (32 B).
Note: When performing DMA transfer in the dual-address mode, a function for automatically negating
DREQ is provided based on the setting of the DBM register.
4.3.4 DMA transfer request
Single-address mode
DMA is started when the CORAL issues an external request to DMAC of the host processor.
Set the transfer count in the transfer count register of the CORAL and then issue DREQ.
Fix the CPU destination address to the FIFO address.
Dual-address mode
DMA is started by two procedures: CORAL issues an external request to DMAC of the host processor,
or the CPU itself is started (auto request mode, etc.). nI Ack use mode, set the transfer count in the
transfer count register of CORAL and then issue DREQ.
Note: In the Ack unused mode and the V832 mode requires no setting of the transfer count register.
4.3.5 Ending DMA transfer
• SH3/SH4
When the CORAL transfer count register is set to 0, DMA transfer ends and DREQ is negated.
• V832
When the XTC signal from the CPU is low-asserted while the DMAAK signal to S CORAL is
high-asserted, the end of DMA transfer is recognized and DREQ is negated.
• The end of DMA transfer is detected in two ways: the DMA status register (DST) is polled, and an
interrupt to end the drawing command (FD000000_H) is added to the display list and the interrupt is
detected.
• In the dual address mode (mode not using ACK), the DMA transfer count register (DTC) is not used, so
the DMA ending cannot be determined. The DREQ signal can be negated to end DMA by writing 1 from
the CPU to the DMA transfer stop register (DTS) of CORAL at DMA transfer end.
MB86293 CORAL_LQ
Graphics Controller
41
Specifications Rev. 1.1