MB86293 Datasheet, PDF (246/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
11.1.9 SH4 single-address DMA write (transfer of 1 long word)
BCLKIN
D[31:0]
DREQ
DRACK
DTACK
Bus cycle
Acceptance
CPU
Acceptance
Acceptance
DMAC
*1
DMAC
CPU *1
¡: DREQ sampling and channel priority determination for SH mode (DREQ = level detection)
*1: In the cycle steal mode, even when DREQ is already asserted at the 2nd DREQ sampling, the
right to use the bus is returned to the CPU temporarily. In the burst mode, DMAC secures the
right to use the bus unless DREQ is negated.
Fig. 10.9 SH4 Single-address DMA Write (Transfer of 1 Long Word)
CORAL writes data according to the DTACK assert timing. When data cannot be received, the DREQ
signal is automatically negated. And then the DREQ signal is reasserted as soon as data reception is
ready.
MB86293 CORAL_LQ
Graphics Controller
246
Specifications Rev. 1.1