MB86293 Datasheet, PDF (37/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
4 HOST INTERFACE
4.1 O p e r a t i o n M o d e
4.1.1 Host CPU mode
Select the host CPU by setting the MODE0 to MODE2 signals as follows:
MODE 2
L
L
L
L
H
MODE 1
L
L
H
H
X
Table 4-1 CPU Type Setting
MODE 0
L
H
L
H
X
SH3
SH4
V832
SPARClite
Reserved
CPU
4.1.2 Ready signal mode
The MODE2 pin can be used to set the ready signal level when the bus cycle of the host CPU terminates.
For the normally not ready mode, set the software wait to 0 or 1 cycles. When using this device in the
normally ready mode, set the software wait to 2 cycles. When using this device in the normally not ready
mode, set the software wait to one cycle. (When BS_MODE = H, three cycles are needed for the
software wait.)
The ‘normally not ready mode’ is the mode in which the CORAL XRDY signal is always in the wait state
and Ready is returned only when read/write is ready.
The ‘normal ready mode’ is the mode in which the CORAL XRDY signal is always in the Ready state and
it is put into the wait state only when read/write cannot be performed immediately.
Table 4-2 Ready Signal Mode
RDY_ MODE
L
H
Ready signal operation
Recognizes XRDY signal as ‘not ready level’ and terminates bus cycle
(normally not ready mode)
Recognizes XRDY signal as ‘ready level’ and terminates bus cycle (normally
ready mode)
MB86293 CORAL_LQ
Graphics Controller
37
Specifications Rev. 1.1