MB86293 Datasheet, PDF (39/285 Pages) Fujitsu Component Limited. – Grraphiics Conttrrollllerr Speciiffiicattiions

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
4.2 A c c e s s M o d e
4.2.1 SRAM interface
Data can be transferred to/from CORAL using SRAM access protocol. CORAL internal registers and
graphics memory are all mapped to the physical address area of the host processor.
CORAL uses hardware wait based on the XRDY signal, enabling the hardware wait setting of the host
CPU. When using the normally not ready mode, set the software wait to “1”. When using the normally
ready mode, set the software wait to “2”. (When using the BS_MODE signal as “High” level, with the
normally ready mode established, set the CPU software wait to three cycles.) Switch the ready mode
using the RDY_ MODE signal.
CPU Read
The host processor reads data from internal registers and memory of CORAL in double-word (32 bit)
units. Valid data is output continuously while XRD and XCS are being asserted at a “Low” level after
XRDY has been asserted.
CPU Write
The host CPU writes data to internal registers and memory of CORAL in byte, word(16 bit) and
double-word( 32 bit) units.
4.2.2 FIFO interface (fixed transfer destination address)
This interface transfers display lists stored in host memory. Display list information is transferred
efficiently using a single address mode DMA transfer. Data can be transferred to FIFO in relation to
FIFO buffer area mapped in memory area using SRAM interface or dual address mode.
MB86293 CORAL_LQ
Graphics Controller
39
Specifications Rev. 1.1