MB86831 Datasheet, PDF (77/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
• The Request Sense Register may contain “1” when the Trigger Mode is changed. Therefore, issue “Request
Clear” before canceling interrupt masks.
The interrupt controller (IRC) and DRAM controller registers cannot be accessed until CS3# becomes“L”.
(9)Cache Invalidate Register
When the caches are off, write to the Cache Invalidate Register.
(10)Internal Clock Control/Status Register
To change clock multiplication by setting the CE bit in the internal clock control/status register to “1”, input the “L”
pulse to the WKUP# pin at least 4000 CLKIN after entering the sleep mode.
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