MB86831 Datasheet, PDF (5/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
6.Register
Register name
MB86831/832/833/835/836
MB86834
Instruction Cache Invalidate
Map of
Map of
Register
ASI = 0x0c, ADR = 0x00001000(Bank1) ASI = 0x0c, ADR = 0x00008000(Bank1)
(ICINVLD)
ASI = 0x0c, ADR = 0x80001000(Bank2) ASI = 0x0c, ADR = 0x80008000(Bank2)
Data Cache Invalidate
Register
(DCINVLD)
Map of
Map of
ASI = 0x0e, ADR = 0x00001000(Bank1) ASI = 0x0e, ADR = 0x00008000(Bank1)
ASI = 0x0e, ADR = 0x80001000(Bank2) ASI = 0x0e, ADR = 0x80008000(Bank2)
Register name
Ancillary Version Register
(VER2)
MB86831
(00)16
MB86832
(01)16
MB86833
(02)16
MB86834
(03)16
MB86835
(04)16
MB86836
(01)16
7.Clock gear
• MB86832/833/834/835/836 : Supported
• MB86831 : No supported
8.External signal
Item
ASISEL pin function
DSU (debugging
support unit)
DRAM controller
General-purpose
16-bit timer
JTAG
Pull-up resistor or
pull-down resistor
MB86831
No
No
4Bank
supported
Inclusion
MB86832 MB86833 MB86834 MB86835 MB86836
Multiplex of
ADR<31:28>
and ASI<3:0>
Multiplex of
ADR<27:24>
and ASI<3:0>
Multiplex of
ADR<31:28>
and ASI<3:0>
Multiplex of ADR<27:24> and
ASI<3:0>
Yes
No
Yes
No
4Bank
supported
1Bank
supported*
No
No
4Bank
supported
1Bank
supported*
No
Wih 1ch.
prescaler
(Equivalent to
MB86942)
Support
Inclusion
No
Inclusion
*:RAS1# to RAS3# and DWE1# to DWE3# deletion.
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