MB86831 Datasheet, PDF (55/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
(7)On-chip interrupt controller
The on-chip interrupt controller accepts interrupt inputs through eight channels, allowing a trigger mode to be set
independently for each of the channels. The interrupt request accepted according to the trigger mode is encoded
and output to the processor.
(8)Multiplier circuit
The MB86830 series incorporates a multiplier circuit which can be selectively set to an operating clock frequency
of x1, x2, x3, x4,or x5 of the external clock frequency, allowing the processor to run at high speed.
(9) Instruction set
The MB86830 series supports high-speed integer multiply instructions which are executed in five, three, and two
cycles respectively for 32-, 16-, and 8-bit multiplications. The integer divide step instruction is near 10 times faster
in divide time than the previous SPARC implementation. The scan instruction supports the function for detecting
1 or 0 at the MSB in a word in a single cycle.
2. CPU
The CPU core of the MB86830 series is a high-performance version implemented by full custom design of the
SPARC architecture. The CPU core contains a compact circuitry for integrating peripheral circuits, designed to be
customizable to a variety of applications. The CPU core consists of three function units: instruction, address, and
execution blocks (see “Integer operation unit internal block diagram”).
The role of five execution stages for instruction pipelining is to decode all instructions and generate control signals
for other blocks. The five pipelined stages are the fetch (F), decode (D), execute (E), memory (M), and write back
(W) stages. The instruction memory returns an instruction addressed at stage (F), the register file returns an op-
erand addressed at stage (D), the ALU perform calculation to obtain the result at stage(E), the external memory is
addressed at stage(M), and the register file is written back at stage (W).
55