MB86831 Datasheet, PDF (15/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
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Symbol
Pin name
NONCACHE#
NON-CACHE-
ABLE
PDOWN#
POWER DOWN
WKUP#
WAKE-UP
BMREQ#
BURST MODE
REQUEST
BMACK#
BURST MODE
ACKNOWL-
EDGE
PBREQ#
PROCESSOR
BUS REQUEST
I/O
Function
Non-cacheable signal.
This pin inputs the signal for exclusion from data caching. The NON-
CACHE# signal is enabled by setting the Cacheability Enable bit (bit 7)
in the Cache/BIU Control Register (CBIR). The “L” input to this pin
when data is read prevents the data and its address from being written
I to the data cache (the NONCACHE# signal is disabled at an instruction
fetch). Usually, the NONCACHE# signal must be asserted in the cycle
in which the address strobe signal is asserted. Even if the NON-
CACHE# signal is asserted after a delay of one or more cycles, how-
ever, the signal can be used by setting the Non-cacheable bit (bit 9, bit
8) in the Cache/BIU Control Register (CBIR).
Sleep mode (low power consumption mode) output pin.
“L” level input to this pin releases the CPU from the sleep mode (low
O power consumption mode) to start operation. Although the pin is an
asynchronous input, it requires an “L” width of at least two clock cycles.
Input “L” to this pin only when the PDOWN# pin is at the “L” level.
Sleep mode (low power consumption mode) cancel pin.
“L” input to this pin cancels the CPU sleep mode (low power consump-
I
tion mode), causing the CPU to start operation. Although the pin is an
asynchronous input, it requires an “L” width of at least two clock cycles.
Input the“L” signal to this pin only when PDOWN# is “L”. When
PDOWN# goes “H”, set this pin to "H".
Burst transfer request pin.
If a cache miss occurs when the Instruction Burst Enable bit or Data
Burst Enable bit in the Bus Control Register (BCR) has been set, the
CPU sets the BMREQ# signal to “L” and requests external memory for
O burst transfer. The BMREQ# signal is also asserted when the DRAM
Burst Enable bit in the System Support Control Register (SSCR) has
been set. In this case, however, the external device need not return
the BMACK# signal because the internal DRAM controller responds to
the request.
Burst mode acknowledge input.
When a burst transfer request is issued, the burst transfer mode is es-
tablished if the “L” level asserted until the same cycle as the READY#
signal is input to this pin. (It is also established either when the “L” level
I is input in the same cycle as the READY# signal or when the “L” level
input in an earlier cycle continues until the same cycle as the READY#
signal.) When the DRAM Burst Enable bit in the System Support Con-
trol Register (SSCR) has been set, the burst transfer mode is estab-
lished even though this pin receives the BMACK# signal.
Processor bus request signal.
When the CPU requires accessing an external bus
O
The PBREQ# signal is asserted to issue a processor bus request to the
external bus master when the CPU requires accessing an external bus
(when it requires external access after a cache miss) while the CPU
has relinquished bus access permission.
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