MB86831 Datasheet, PDF (62/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
(4)Y Register (Y)
bit→ 31
0
(5)Ancillary State Register 17 (ASR17)
bit→ 31
Reserved
bit 31 to bit 1 :Reserved [“0”Write, Don’t care for read]
bit 0
:Single Vector Trapping [SVT] (Enable = 1, Disable = 0, RST = 0)
10
SVT
13. IU (Integer Unit) General-Purpose Registers (Not Memory Mapped)
The IU (integer unit) contains 136 32-bit general-purpose registers for holding arguments for operations and their
results. Of these registers, only 32 registers can be accessed through blocks called register windows.
The integer unit has eight register windows. The register window to be used is determined by the CWP bits (bits
2 to 0) in the Processor Status Register (PSR). Each register window consists of eight global registers available
commonly to all register windows and 24 registers (in-register × 8, local register × 8, out-register × 8). The in-reg-
isters and out-registers are used commonly between adjacent register windows.
(1)Zero Register (r0)
bit→ 31
0
0
bit 31 to bit 0 :0
(2)General register (r1 to r31)
bit→ 31
0
Don’t care at reset.
14. Bit map of register with built-in CPU core
(1)Cache/BIU Control Register (CBIR)
bit→ 31
Reserved
ASI= 0x01, Address= 0x00000000H
10 9 8 7 6 5 4 3 2 1 0
bit 31 to bit 10 :Reserved [“0”Write, Don’t care for read]
bit 9 to bit 8 :Non-cacheable Wait-state [Don’t care for read]
bit 7
:Cacheability Enable [Don’t care for read] (Enable = 1, Disable = 0, RST = 0)
bit 6
:Reserved [“0”Write, Don’t care for read]
bit 5
:Write Buffer Enable (Enable = 1, Disable = 0, RST = 0)
bit 4
:Prefetch Buffer Enable (Enable = 1, Disable = 0, RST = 0)
bit 3
:Data Cache Lock (Lock = 1, Unlock = 0, RST = 0)
bit 2
:Data Cache Enable (Enable = 1, Disable = 0, RST = 0)
bit 1
:Instruction Cache Lock (Lock = 1, Unlock = 0, RST = 0)
bit 0
:Instruction Cache Enable (Enable = 1, Disable = 0, RST = 0)
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