MB86831 Datasheet, PDF (68/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
(5)Instruction Cache Data RAM (ICDATA)
bit→ 31
bit 31 to bit 0:Data (RST = X)
X:Don’t care
ASI = 0x0d
Capacity 16 KB
Bank 1:Address = 0x00000000H to 0x00001ffcH (+4)
Bank 2:Address = 0x80000000H to 0x80001ffcH (+4)
Capacity 8 KB
Bank 1:Address = 0x00000000H to 0x00000ffcH (+4)
Bank 2:Address = 0x80000000H to 0x80000ffcH (+4)
Capacity 4 KB
Bank 1:Address = 0x00000000H to 0x000007fcH (+4)
Bank 2:Address = 0x80000000H to 0x800007fcH (+4)
Capacity 2 KB
Bank 1:Address = 0x00000000H to 0x000003fcH (+4)
Bank 2:Address = 0x80000000H to 0x800003fcH (+4)
Capacity 1 KB
Bank 2:Address = 0x80000000H to 0x800003fcH
0
Data
(6)Data Cache Tag (DCTAG)
bit→ 31
Address Tag
ASI = 0x0e
Capacity 16 KB
Bank 1:Address = 0x00000000H to 0x00001fe0H (+32)
Bank 2:Address = 0x80000000H to 0x80001fe0H (+32)
Capacity 8 KB
Bank 1:Address = 0x00000000H to 0x00000fe0H (+32)
Bank 2:Address = 0x80000000H to 0x80000fe0H (+32)
Capacity 4 KB
Bank 1:Address = 0x00000000H to 0x000007e0H (+32)
Bank 2:Address = 0x80000000H to 0x800007e0H (+32)
Capacity 2 KB
Bank 1:Address = 0x00000000H to 0x000003f0H(+16)
Bank 2:Address = 0x80000000H to 0x800003f0H (+16)
Capacity 1 KB
Bank 2:Address = 0x80000000H to 0x800003f0H (+16)
13 12 11 10 9
654
210
bit 31 to bit 13 :Address Tag (RST = X)
bit 12
:Capacity 16 KB = <Reserved>, Other = <Address Tag>
bit 11
:Capacity 16 KB, 8 KB = <Reserved>, Other = <Address Tag>
bit 10
:Capacity 16 KB, 8 KB, 4 KB = <Sub Block Valid>(Valid = 1, Invalid = 0, RST = 0)
Capacity 2 KB, 1 KB = <Address Tag>
bit 9 to bit 6 :Sub Block Valid (Valid = 1, Invalid = 0,RST = 0)
bit 4 to bit 2 :Capacity 16 KB, 8 KB, 4 KB = <Sub Block Valid>(Valid = 1, Invalid = 0, RST = 0)
Capacity 2 KB, 1 KB = <Reserved>[Don’t care for read]
bit 5
:User/Supervisor (User = 1, Supervisor = 0, RST = X)
bit 1
:Capacity 1 KB = <Reserved>, Other = LRU (RST = 0) *
bit 0
:Entry Lock (Lock = 1, Unlock = 0, RST = 0)
*:BANK 1 only, BANK 2 is Reserved
X:Don’t care
68