MB86831 Datasheet, PDF (75/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
(2) Timer Control Register (TCR)
CS3# = L, Address<9:2> = 0x0d
bit→ 31
16 15 14 13 12 11 10 9 8 7 6 5
32
0
Reserved
bit 31 to bit 16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10 to bit 9
bit 8 to bit 7
bit 6
bit 5 to bit 3
bit 2 to bit 0
:Reserved [“0”Write, Don’t care for read]
:Value Of OUT Signal
:Value Of IN Signal
:Reserved [“0”Write, Don’t care for read]
:Test [“0”Write]
:Count Enable (Enable = 1, Disable = 0, RST = 0)
:Clock Select (Internal Clock = 0, Prescaler Clock = 2, Don’t Use = 1 or 3, RST = 0)
:OUT Signal Control (Keep = 0, Set = 1, Reset = 2, Don’t Use = 3)
:Invert (true = 0, Invert = 1, RST = 0)
:Mode Select
:Event Select
(3) Reload Value Register (RVR)
bit→ 31
16 15
Reserved
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 0 :Reload Value
CS3# = L, Address<9:2> = 0x0e
0
Reload Value
(4) Count Value Register (CVR) [Read Only]
CS3# = L, Address<9:2> = 0x0f
bit→ 31
16 15
0
Reserved
Count Value
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 0 :Count Value
For details on each register, refer to the manual for the MB86942.
21. Notes on Register Setting
(1)Cache/BIU Control Register
• To set Cache Enable or Cache Disable, be sure to insert at least three NOP instructions after the Enable or
Disable instruction.
• The Non-Cacheable bit (bit 9, bit 8) and Cacheability Enable bit (bit 7) cannot be read.
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