MB86831 Datasheet, PDF (73/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
bit 3
0
0
1
1
bit 2
0
1
0
1
Type
Break only on Loads
Break only on Stores
Break on Load or Store
Break Always
bit 1
:Data Value Condition (Outside = 1, Inside = 0, RST = 0)
bit 0
:Data Value Mask (Mask = 1, Range = 0, RST = 0)
(6)Debug Status Register (DSR)
ASI = 0x01, Address = 0x0000ff1CH
bit→ 31
Reserved
6543210
bit 31 to bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
:Reserved [“0”Write, Don’t care for read]
:Data Address 2 Match (Match = 1, Not Match = 0, RST = 0)
:Data Address 1 Match (Match = 1, Not Match = 0, RST = 0)
:Instruction Address 2 Match (Match = 1, Not Match = 0, RST = 0)
:Instruction Address 1 Match (Match = 1, Not Match = 0, RST = 0)
:EMUENBL [Read only]
:EMUBRK [Read only]
19. Clock gear (Not supported in MB86831-66,80)
Internal Clock Control/Status Register (ICCS)
CS3# = L, Address<9:2> = 0x0b
bit→ 31
Reserved
76
432
0
CLKST CE CLKSEL
bit 31 to bit 7
bit 6 to bit 4
bit 3
bit 2 to bit 0
:Reserved [“0”Write, Don’t care for read]
:Internal Clock Status [CLKST]
:Internal Clock Change Enable [CE] (Enable = 1, Disable = 0, RST = 0)
:Internal Clock Select [CLKSEL]
CLKST
Internal Clock
100
×1
101
×2
110
×3
111
×4
011
×5
010
001
Reserved
000
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