MB86831 Datasheet, PDF (17/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
2. DRAM Controller Related Pins (MB86831/832/833/834/835)
Symbol
Pin name
I/O
Function
RAS0#
RAS1#
RAS2#
RAS3#
DRAM ROW
ADDRESS
STROBE
DRAM controller RAS outputs.
The RAS0# to RAS3# signals are control signals corresponding to
O DRAM banks 0 to 3, respectively.
The MB86833/835 does not support banks 1 to 3 because the RAS1#
to RAS3# pins do not exist on the chip.
CAS0#
CAS1#
CAS2#
CAS3#
DRAM COLUMN
ADDRESS
STROBE
DRAM CAS control outputs.
For using the 32-bit bus width along with 2-CAS DRAM, the CAS0# to
CAS3# pins are controlled in association with byte 0 (b31 to b24), byte
1 (b23 to b16), byte 2 (b15 to b8), and byte 3 (b7 to b0), respectively.
For using the 16-bit bus width along with 2-CAS DRAM, the CAS2# and
O CAS3# pins correspond to byte 0 (byte data at an even-numbered ad-
dress) and byte 1 (byte data at an odd-numbered address), respective-
ly. When the 16-bit bus width is used, the outputs from the CAS0# and
CAS1# pins are unpredictable.
When 2-WE DRAM is used, the CAS0# to CAS3# pins provide the
same output.
DWE0#
DWE1#
DWE2#
DWE3#
DRAM WRITE
ENABLE
DRAM write enable control outputs.
For using 2-WE DRAM, the DWE0# to DWE3# signals are controlled in
association with byte 0 (b31 to b24), byte 1 (b23 to b16), byte 2 (b15 to
O b8), and byte 3 (b7 to b0), respectively.
When 2-CAS DRAM is used, the DWE0# to DWE3# pins provide the
same output.
The DWE1# to DWE3# pins do not exist on the MB86833/835.
DOE#
DRAM OUTPUT
DRAM OE control output.
When fast-page DRAM is used, the DRAM can be controlled without
O
using the DOE# signal because the DWEx# and CASx# pins are con-
trolled at the early write timing. When EDO (hyper page mode) DRAM
is used, the DOE# signal is required for high-impedance control of the
DRAM output.
ADR<13:2>
ADDRESS BUS
DRAM address signal.
I/O The DRAM controller outputs the multiplexed row and column address-
es to a CPU address pin of ADR<13:2>.
• State of pins
Pin symbol
At reset
At bus grant
Pin symbol
At reset At bus grant
RAS3# to RAS0#
O (H)
O (V)
CAS3# to CAS0#
O (H)
O (V)
DOE#
O (H)
O (V)
ADR<13:2>
O (X)
I (D)
O (V) : The circuit is active with the output at a valid level.
O (X) : The circuit is inactive with the output indeterminate.
O (H) : The “H” level is output.
I (D) : When the DRAM controller has been enabled, the pin is switched to serve as an output, from the clock cycle
that follows the clock cycle in which the AS# pin becomes “L”, and remains as the output until the ready
signal input pin becomes “L”. When the DRAM controller has been disabled, the pin enters the High-Z
state.
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