MB86831 Datasheet, PDF (71/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
(6)IRL Latch/Clear Register (IRLAT)
bit→ 31
Reserved
16 15
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 5 :Reserved [“0”Write, Read"0"]
bit 4
:IRL Clear [Wite only] (Clear = 1, Not Clear = 0)
bit 3 to bit 0 :IRL Latch [Read only] (RST = 0000)
CS3# = L, Address<9:2> = 0x05
Reserved
543
0
CL
IRL
(7)IRC Mode Register (IMODE)
CS3# = L, Address<9:2> = 0x06
bit→ 31
Reserved
16 15
Reserved
21 0
IRCMD
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 2 :Reserved [“0”Write, Read“0”]
bit 1 to bit 0 :IRC Mode [IRCMD] (Disable = 00, Enable = 01, RST = 00)
17. DRAM controller
(1)DRAM Bank Configuration Register (DBANKR)
CS3# = L, Address<9:2> = 0x08
bit→
31
ERR
Reserved
11 10 9 8 7 6
43
0
STADR HE TP COL
BKSIZE
bit 31
:Access Error [ERR] (Error = 1, No Error = 0, RST = X, “0”Write Clear)
bit 30 to bit 11 :Reserved [“0”Write, Don’t care for read]
bit 10 to bit 9 :DRAM Start Address [STADR] (RST = 01)
bit 8
:Hyper Page Enable [HE] (Page Mode DRAM = 0, EDO DRAM = 1, RST = 0)
bit 7
:DRAM Type[TP] (4CAS-1WE= 0, 4WE -1CAS = 1, RST = 0)
bit 6 to bit 4 :Column Address [COL] (RST = 011)
bit 3 to bit 0 :Bank Size [BKSIZE] (RST = 0011)
X:Don’t care
(2)DRAM Timing Register (DTIMR)
CS3# = L, Address<9:2> = 0x09
bit→ 31
Reserved
54
TRPS
32
TRASCBR
10
TCAS TRP
bit 31 to bit 5
bit 4
bit 3 to bit 2
bit 1
bit 0
:Reserved [“0”Write, Don’t care for read]
:RAS#Precharge time specification bits [TRPS] at Self-Refresh (2 Cycle = 0, 4 Cycle = 1, RST = 1)
:RAS#Pulse width specification bit [TRASCBR] at CBR Refresh
(1 Cycle = 00, 2 Cycle = 01, 3 Cycle = 10, RST = 01)
:CAS#Pulse width specification bit [TCAS] (1 Cycle = 0, 2 Cycle = 1, RST = 1)
:RAS#Precharge width specification bit [TRP] (1 Cycle = 0, 2 Cycle = 1, RST = 0)
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